In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. This capability is well-suited to performing analog-to-digital conversion using pipeline algorithms, among other applications.
Charge-domain signal-processing circuits are implemented as charge-coupled devices (CCDs), as MOS bucket-brigade devices (BBDs), and as bipolar BBDs. Embodiments of the present invention pertains to MOS and bipolar BBDs.
In differential BBD-based pipelined signal-processing circuits, the signal at each pipeline stage is represented as the difference between a pair of charges, each of which is processed in a separate pipeline. At each stage the charge-pair has a differential-charge component representing the signal, and a common-mode or bias charge component. The differential component is altered at each stage in accordance with the signal-processing algorithm which is being implemented. The common-mode component changes from each stage to the next by a nominally fixed amount, independent of the arriving differential signal charge.